HIGH SPEED SERDES (INTRODUCTION)

(25:42)

SERDES LAYOUT (WIRE / INTERCONNECT PARASITICS)

(27:58)

SerDes (Serializer/Deserializer) Explained in 5 Minutes

(4:44)

Addressing Challenges with Large SerDes System Designs — Mentor

(30:12)

High-speed layout guidelines for reducing EMI in LVDS SerDes designs

(8:17)

SerDes Basics

(3:27)

Concepts in High Speed SERDES - Transmitter

(58:14)

What is a SerDes and why do I need one?

(7:40)

ChannelExpert: Analysis of Pre-Layout SerDes Channel

(8:12)

SERDES Clocking and Equalization for High-Speed Serial Links, Jack Kenney

(12:21)

SerDes Design and Verification for PAM3 and PAM4 High-Speed Digital Links

(20:30)

CTLE (Continuous Time Linear Equalizer) : HIGH SPEED SERDES

(14:34)

High Speed Communications Part 9 – Anatomy of a Modern SerDes

(6:46)

Next Generation PAM4 SerDes Development with Microchip's Mixed-Signal Development Group

(1:26)